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rev. d information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD820 one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 single supply, rail to rail low power fet-input op amp functional block diagram features true single supply operation output swings rail-to-rail input voltage range extends below ground single supply capability from 5 v to 36 v dual supply capability from 2.5 v to 18 v excellent load drive capacitive load drive up to 350 pf minimum output current of 15 ma excellent ac performance for low power 800 a max quiescent current unity gain bandwidth: 1.8 mhz slew rate of 3.0 v/ s excellent dc performance 800 v max input offset voltage 1 v/ c typ offset voltage drift 25 pa max input bias current low noise 13 nv/ hz @ 10 khz applications battery-powered precision instrumentation photodiode preamps active filters 12- to 14-bit data acquisition systems medical instrumentation low power references and regulators product description the AD820 is a precision, low power fet input op amp that can operate from a single supply of 5.0 v to 36 v, or dual sup- plies of 2.5 v to 18 v. it has true single supply capability with an input voltage range extending below the negative rail, 50 0 10 15 5 1 10 0 30 20 25 35 40 45 9 8 7 6 5 4 3 2 input bias current ?pa number of units figure 1. typical distribution of input bias current allowing the AD820 to accommodate input signals below ground in the single supply mode. output voltage swing extends to w ithin 10 mv of each rail providing the maximum output dynamic range. offset voltage of 800 v max, offset voltage drift of 1 v/ c, typical input bias currents below 25 pa and low input voltage noise provide dc precision with source impedances up to a gigaohm. 1.8 mhz unity gain bandwidth, ?3 db thd at 10 khz and 3 v/ s slew rate are provided for a low supply current of 800 a. the AD820 drives up to 350 pf of direct capacitive load and provides a minimum output current of 15 ma. this allows the amplifier to handle a wide range of load conditions. this combi- nation of ac and dc performance, plus the outstanding load drive capability, results in an exceptionally versatile amplifier for the single supply user. the AD820 is available in two performance grades. the a and b grades are rated over the industrial temperature range of ?0 c to +85 c. the AD820 is offered in two varieties of 8-lead package: plastic dip, and surface mount (soic). figure 2. gain of 2 amplifier; v s = 5, 0, v in = 2.5v sine centered at 1.25 volts 1 2 3 4 8 7 6 5 top view (not to scale) AD820 null ?n +in ? s nc +v s v out null 1 2 3 4 8 7 6 5 top view (not to scale) AD820 nc ?n +in ? s nc +v s v out nc nc = no connect
rev. d ?2? AD820especifications AD820a AD820b parameter conditions min typ max min typ max unit dc performance initial offset 0.1 0.8 0.1 0.4 mv max offset over temperature 0.5 1.2 0.5 0.9 mv offset drift 2 2 v/ c input bias current v o = 0 v to 4 v 2 25 2 10 pa at t max 0.5 5 0.5 2.5 na input offset current 2 20 2 10 pa at t max 0.5 0.5 na open-loop gain v o = 0.2 v to 4 v t min to t max r l = 100 k 400 1000 500 1000 v/mv 400 400 v/mv t min to t max r l = 10 k 80 150 80 150 v/mv 80 80 v/mv t min to t max r l = 1 k 15 30 15 30 v/mv 10 10 v/mv noise/harmonic performance input voltage noise 0.1 hz to 10 hz 2 2 v p-p f = 10 hz 25 25 nv/ hz hz hz hz hz hz hz hzhz hz hz h hz hz hz h 0.5 10 13 0.5 pf common mode 10 13 2.8 10 13 2.8 pf output characteristics output saturation voltage 2 v ol ev ee i sink = 20 a57 57mv t min to t max 10 10 mv v cc ev oh i source = 20 a10141 014mv t min to t max 20 20 mv v ol ev ee i sink = 2 ma 40 55 40 55 mv t min to t max 80 80 mv v cc ev oh i source = 2 ma 80 110 80 110 mv t min to t max 160 160 mv v ol ev ee i sink = 15 ma 300 500 300 500 mv t min to t max 1000 1000 mv v cc ev oh i source = 15 ma 800 1500 800 1500 mv t min to t max 1900 1900 mv operating output current 15 15 ma t min to t max 12 12 ma short-circuit current 25 25 ma capacitive load drive 350 350 pf power supply quiescent current t min to t max 620 800 620 800 a power supply rejection v s + = 5 v to 15 v 70 80 66 80 db t min to t max 70 66 db (v s = 0, 5 v @ t a = 25 c, v cm = 0 v, v out = 0.2 v unless otherwise noted.)
rev. d ?3? AD820 specifications AD820a AD820b parameter conditions min typ max min typ max unit dc performance initial offset 0.1 0.8 0.3 0.4 mv max offset over temperature 0.5 1.5 0.5 1 mv offset drift 2 2 v/ c input bias current v o = e5 v to 4 v 2 25 2 10 pa at t max 0.5 5 0.5 2.5 na input offset current 2 20 2 10 pa at t max 0.5 0.5 na open-loop gain v o = 4 v to e4 v r l = 100 k 400 1000 400 1000 v/mv t min to t max 400 400 v/mv r l = 10 k 80 150 80 150 v/mv t min to t max 80 80 v/mv r l = 1 k 20 30 20 30 v/mv t min to t max 10 10 v/mv noise/harmonic performance input voltage noise 0.1 hz to 10 hz 2 2 v p-p f = 10 hz 25 25 nv/ hz hz hz hz hz hz hz hzhz hz hz h hz hz hz h 0.5 10 13 0.5 pf common mode 10 13 2.8 10 13 2.8 pf output characteristics output saturation voltage 2 v ol ev ee i sink = 20 a57 57mv t min to t max 10 10 mv v cc ev oh i source = 20 a10141 014mv t min to t max 20 20 mv v ol ev ee i sink = 2 ma 40 55 40 55 mv t min to t max 80 80 mv v cc ev oh i source = 2 ma 80 110 80 110 mv t min to t max 160 160 mv v ol ev ee i sink = 15 ma 300 500 300 500 mv t min to t max 1000 1000 mv v cc ev oh i source = 15 ma 800 1500 800 1500 mv t min to t max 1900 1900 mv operating output current 15 15 ma t min to t max 12 12 ma short-circuit current 30 30 ma capacitive load drive 350 350 pf power supply quiescent current t min to t max 650 800 620 800 a power supply rejection v s + = 5 v to 15 v 70 80 70 80 db t min to t max 70 70 db (v s = 0, 5 v @ t a = 25 c, v cm = 0 v, v out = 0.2 v unless otherwise noted.)
rev. d ?4? AD820especifications AD820a AD820b parameter conditions min typ max min typ max unit dc performance initial offset 0.4 2 0.3 1.0 mv max offset over temperature 0.5 3 0.5 2 mv offset drift 2 2 v/ c input bias current v cm = 0 v 2 25 2 10 pa v cm = e10 v 40 40 pa at t max v cm = 0 v 0.5 5 0.5 2.5 na input offset current 2 20 2 10 pa at t max 0.5 0.5 na open-loop gain v o = +10 v to e10 v r l = 100 k 500 2000 500 2000 v/mv t min to t max 500 500 v/mv r l = 10 k 100 500 100 500 v/mv t min to t max 100 100 v/mv r l = 1 k 30 45 30 45 v/mv t min to t max 20 20 v/mv noise/harmonic performance input voltage noise 0.1 hz to 10 hz 2 2 v p-p f = 10 hz 25 25 nv/ hz hz hz hz hz hz hz hzhz hz hz h hz hz hz h 0.5 10 13 0.5 pf common mode 10 13 2.8 10 13 2.8 pf output characteristics output saturation voltage 2 v ol ev ee i sink = 20 a57 57mv t min to t max 10 10 mv v cc ev oh i source = 20 a10141 014mv t min to t max 20 20 mv v ol ev ee i sink = 2 ma 40 55 40 55 mv t min to t max 80 80 mv v cc ev oh i source = 2 ma 80 110 80 110 mv t min to t max 160 160 mv v ol ev ee i sink = 15 ma 300 500 300 500 mv t min to t max 1000 1000 mv v cc ev oh i source = 15 ma 800 1500 800 1500 mv t min to t max 1900 1900 mv operating output current 20 20 ma t min to t max 15 15 ma short-circuit current 45 45 ma capacitive load drive 350 350 power supply quiescent current t min to t max 700 900 700 900 a power supply rejection v s + = 5 v to 15 v 70 80 70 80 db t min to t max 70 70 db (v s = 15 v @ t a = 25 c, v cm = 0 v, v out = 0 v unless otherwise noted.)
rev. d ?5? AD820 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD820 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. notes 1 this is a functional specification. amplifier bandwidth decreases when the input common-mode voltage is driven in the range (+ v s e 1 v) to +v s . common-mode error voltage is typically less than 5 mv with the common-mode voltage set at 1 volt below the positive supply. 2 v ol ev ee is defined as the difference between the lowest possible output voltage (v ol ) and the minus voltage supply rail (v ee ). v cc ev oh is defined as the difference between the highest possible output voltage (v oh ) and the positive supply voltage (v cc ) . specifications subject to change without notice. absolute maximum ratings 1 supply voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 v internal power dissipation 2 plastic dip (n) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.6 w soic (r) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0 w input voltage . . . . . . . . . . . . . . (+v s + 0.2 v) to e (20 v + v s ) output short circuit duration . . . . . . . . . . . . . . . . indefinite differential input voltage . . . . . . . . . . . . . . . . . . . . . . . 30 v storage temperature range (n) . . . . . . . . . e65 c to +125 c storage temperature range (r) . . . . . . . . . e65 c to +150 c operating temperature range AD820a/b . . . . . . . . . . . . . . . . . . . . . . . . . e40 c to +85 c lead temperature range (soldering 60 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 8-lead plastic dip package: ja = 90 c/w 8-lead soic package: ja = 160 c/w ordering guide temperature package package model range description options AD820an e40 c to +85 c 8-lead plastic mini-dip n-8 AD820bn * e40 c to +85 c 8-lead plastic mini-dip n-8 AD820ar e40 c to +85 c 8-lead soic r-8 AD820br e40 c to +85 c 8-lead soic r-8 warning! esd sensitive device * not for new design, obsolete april 2002.
rev. d ?6? AD820 0.5 50 0 0 30 10 e0.4 20 e0.5 40 0.4 0.3 0.2 0.1 e0.1 e0.2 e0.3 offset voltage e mv number of units v s = 0v, 5v tpc 1. typical distribution of offset voltage (248 units) v s = 5v v s = 15v offset voltage drift e v/ c 48 0 10 24 8 e8 16 e10 40 32 8 4 2 06 e2 e4 e6 % in bin tpc 2. typical distribution of offset voltage drift (120 units) 50 0 10 15 5 1 10 0 30 20 25 35 40 45 9 8 7 6 5 4 3 2 input bias current e pa number of units tpc 3. typical distribution of input bias current (213 units) input bias current e pa 5 0 e5 e5 e4 5 4 3 2 1 0 e1 e2 e3 common-mode voltage e v v s = 5v v s = 0v, +5v and 5v tpc 4. input bias current vs. common-mode voltage; v s = +5 v, 0 v and v s = 5 v input bias current e pa common-mode voltage e v 1k 10 0.1 e16 e12 16 12 8 4 0 e4 e8 100 1 tpc 5. input bias current vs. common-mode voltage; v s = 15 v 100k 100 0.1 20 40 140 120 100 80 60 1k 10k 1 10 temperature e c input bias current e pa tpc 6. input bias current vs. temperature; v s = 5 v, v cm = 0 etypical performance characteristics
rev. d ?7? AD820 v s = 15v 10m 100k 10k 100 1k 100k 10k 1m load resistance e open-loop gain ev/v v s = 0v, 5v tpc 7. open-loop gain vs. load resistance r l = 10k r l = 100k 140 10m 100k 10k 1m e60 e40 120 100 80 60 40 20 0 e20 temperature e c open-loop gain e v/v r l = 600 v s = 0v, 5v v s = 0v, 5v v s = 0v, 5v v s = 15v v s = 15v v s = 15v tpc 8. open-loop gain vs. temperature r l = 100k r l = 600 300 e300 16 0 e200 e12 e100 e16 200 100 12 4 0 e4 8 e8 output voltage e v input voltage e v r l = 10k tpc 9. input error voltage vs. output voltage for resistive loads neg rail pos rail r l = 2k r l = 20k pos rail r l = 100k 40 e40 0 300 20 e20 60 0 180 240 120 output voltage from voltage rails e mv input voltage e v neg rail neg rail pos rail tpc 10. input error voltage with output voltage within 300 mv of either supply rail for various resistive loads; v s = 5 v 1k 100 1 10 10k 1k 100 1 frequency e hz 10 input voltage noise e nv/ hz tpc 11. input voltage noise vs. frequency r l = 10k a cl = e1 v s = 0v, 5v; v out = 4.5v p-p v s = 5v; v out = 9v p-p e40 e90 e110 100 1k 100k 10k e60 e100 e80 e70 e50 frequency e hz thd e db v s = 15v; v out = 20v p-p tpc 12. total harmonic distortion vs. frequency
rev. d ?8? AD820 100 40 e20 10 100 10m 1m 100k 10k 1k 60 80 0 20 frequency e hz open-loop gain e db 100 40 e20 60 80 0 20 phase margin in degrees gain phase r l = 2k c l = 100pf tpc 13. open-loop gain and phase margin vs. frequency a cl = +1 v s = 15v 1k 100 0.01 100 1k 10m 1m 100k 10k 10 1 0.1 frequency e hz output impedance e tpc 14. output impedance vs. frequency 1% 1% error 0.01% 0.1% 16 e16 5.0 e8 e12 1.0 0.0 0 e4 4 8 12 4.0 3.0 2.0 settling time e s output swing from 0 to volts tpc 15. output swing and error vs. settling time 100 50 0 10 100 10m 1m 100k 10k 1k 60 70 80 90 10 20 30 40 frequency e hz common-mode rejection e db v s = 0v, 5v v s = 15v tpc 16. common-mode rejection vs. frequency positive rail +125 c +125 c +25 c negative rail e55 c common-mode voltage from supply rails e v common-mode error voltage e mv 5 0 3 3 1 2 e1 4 2 1 0 e55 c tpc 17. absolute common-mode error vs. common-mode voltage from supply rails (v s ? v cm ) v ol e v s 1000 100 0 0.001 0.01 100 10 1 0.1 10 load current e ma output saturation voltage e mv v s e v oh tpc 18. output saturation voltage vs. load current
rev. d ?9? AD820 i source = 10ma i sink = 10ma i source = 1ma i sink = 1ma i source = 10 a i sink = 10 a 1000 100 1 e60 e40 140 120 100 80 60 40 20 0 e20 10 temperature e c output saturation voltage e mv tpc 19. output saturation voltage vs. temperature eout v s = 15v v s = 15v v s = 0v, 5v temperature e c short circuit current limit e ma 80 0 140 20 10 e40 e60 40 30 50 60 70 120 100 80 60 40 20 0 e20 + e + v s = 0v, 5v tpc 20. short circuit current limit vs. temperature t = +125 c t = +25 c t = e55 c total supply voltage e v quiescent current e a 800 0 36 200 100 4 0 400 300 500 600 700 30 28 24 20 16 12 8 tpc 21. quiescent current vs. supply voltage vs. temperature frequency e hz power supply rejection e db 120 60 0 10 100 10m 1m 100k 10k 1k 30 90 80 20 50 110 70 10 40 100 epsrr +psrr tpc 22. power supply rejection vs. frequency r1 = 2k frequency e hz output voltage e v 30 15 0 10k 100k 10m 1m 10 5 20 25 v s = 15v v s = 0v, 5v tpc 23. large signal frequency response
rev. d ?10? AD820 figure 6. large signal response unity gain follower; v s = 15 v, r l = 10 k figure 7. small signal response unity gain follower; v s = 15 v, r l = 10 k gnd figure 8. v s = 5 v, 0 v; unity gain follower response to 0 v to 5 v step AD820 r l 100pf v out 0.01 f +v s v in 0.01 f ev s 3 2 4 7 6 figure 3. unity gain follower figure 4. 20 v, 25 khz sine input; unity gain follower; r l = 600 , v s = 15 v gnd figure 5. v s = 5 v, 0 v; unity gain follower response to 0 v to 4 v step
rev. d ?11? AD820 gnd figure 12. v s = 5 v, 0 v; unity gain follower response to 40 mv step centered 40 mv above ground 100 gnd figure 13. v s = 5 v, 0 v; gain-of-two inverter response to 20 mv step, centered 20 mv below ground AD820 r l 100pf v out 0.01 f +v s v in 3 2 4 7 6 figure 9. unity gain follower 10k 20k v in AD820 r l 100pf v out 0.01 f +v s 3 2 4 7 6 figure 10. gain of two inverter gnd figure 11. v s = 5 v, 0 v; gain-of-two inverter response to 2.5 v step centered ?1.25 v below ground
rev. d ?12? AD820 application notes input characteristics in the AD820, n-channel jfets are used to provide a low off set, l ow noise, high impedance input stage. minimum input common- mode voltage extends from 0.2 v below ev s to 1 v less than +v s . driving the input voltage closer to the positive rail will cause a loss of amplifier bandwidth (as can be seen by comparing the large signal responses shown in figures 5 and 8) and increased common-mode voltage error as illustrated in tpc 11. the AD820 does not exhibit phase reversal for input voltages up to and including +v s . figure 14a shows the response of an AD820 voltage follower to a 0 v to 5 v (+v s ) square wave input. the input and output are superimposed. the output polarity tracks the input polarity up to +v s ?no phase reversal. the reduced bandwidth above a 4 v input causes the rounding of the output wave form. for input voltages greater than +v s , a resistor in series with the AD820?s plus input will prevent phase reversal, at the expense of greater input voltage noise. this is illustrated in figure 14b. since the input stage uses n-channel jfets, input current during normal operation is negative; the current flows out from the input terminals. if the input voltage is driven more positive than +v s e 0.4 v, the input current will reverse direction as internal de vice junctions become forward biased. this is illustrated in tpc 4. r p AD820 v out v in +5v gnd (a) +v s gnd (b) figure 14. (a) response with r p = 0; v in from 0 to +v s figure 36. (b) v in = 0 to +v s + 200 mv v out = 0 to +v s r p = 49.9 k a current limiting resistor should be used in series with the input of the AD820 if there is a possibility of the input voltage exceeding the positive supply by more than 300 mv, or if an input voltage will be applied to the AD820 when v s = 0. the amplifier will be damaged if left in that condition for more than 10 seconds. a 1 k resistor allows the amplifier to withstand up to 10 volts of continuous overvoltage, and increases the input voltage noise by a negligible amount. input voltages less than ev s are a completely different story. the amplifier can safely withstand input voltages 20 v below the minus supply voltage as long as the total voltage from the posi tive supply to the input terminal is less than 36 v. in addition, the input stage typically maintains picoamp level input currents across that input voltage range. the AD820 is designed for 13 nv/ hz hz h hhh hz hz
rev. d ?13? AD820 direct capacitive load will interact with the amplifier?s effective output impedance to form an additional pole in the amplifier?s feedback loop, which can cause excessive peaking on the pulse response or loss of stability. worst case is when the amplifier is used as a unity gain follower. figure 16 shows the AD820?s pulse response as a unity gain follower driving 350 pf. this amount of over shoot indicates approximately 20 degrees of phase margin?the system is stable, but is nearing the edge. configurations with less loop gain, and as a result less loop bandwidth, will be much less sensi- tive to capacitance load effects. figure 17 is a plot of capacitive load that will result in a 20 degree phase margin versus noise gain for the AD820. noise gain is the inverse of the feedback attenue ation factor provided by the feedback network in use. figure 16. small signal response of AD820 as unity gain follower driving 350 pf capacitive load r i r f capacitive load for 20 phase margin e pf 5 4 1 300 noise gain e 1+ r f r i 3 2 1k 3k 10k 30k figure 17. capacitive load tolerance vs. noise gain figure 18 shows a possible configuration for extending capaci- tance load drive capability for a unity gain follower. with these component values, the circuit will drive 5,000 pf with a 10% overshoot. 100 20k AD820 v out 0.01 f +v s v in 0.01 f ev s 3 2 4 7 6 20pf figure 18. extending unity gain follower capacitive load capability beyond 350 pf offset voltage adjustment the AD820?s offset voltage is low, so external offset voltage null- ing is not usually required. figure 19 shows the recommended technique for AD820?s packaged in plastic dips. adjusting offset voltage in this manner will change the offset voltage temperature drift by 4 v/ c for every millivolt of induced offset. the null pins are not functional for AD820s in the so-8 r package. 20k 1 AD820 +v s ev s 3 2 4 7 6 5 figure 19. offset null applications single supply half-wave and full-wave rectifiers an AD820 configured as a unity gain follower and operated with a single supply can be used as a simple half-wave rectifier. the AD820?s inputs maintain picoamp level input currents even when driven well below the minus supply. the rectifier puts that behav- ior to good use, maintaining an input impedance of over 10 11 for input voltages from 1 volt from the positive supply to 20 volts below the negative supply. the full and half-wave rectifier shown in figure 20 operates as follows: when v in is above ground, r1 is bootstrapped through the unity gain follower a1 and the loop of amplifier a2. this forces the inputs of a2 to be equal, thus no current flows through r1 or r2, and the circuit output tracks the input. when v in is below ground, the output of a1 is forced to ground. the nonin verting input of amplifier a2 sees the ground level output of a1, therefore, a2 oper- ates as a unity gain inverter. the output at node c is then a full-wave rectified version of the input. node b is a buffered half-wave rectified version of the input. input voltages up to 18 volts can be rectified, depending on the voltage sup ply used.
rev. d ?14? AD820 r1 100k AD820 2 3 6 full-wave rectified output half-wave rectified output r2 100k a c b AD820 0.01 f +v s v in 3 2 4 7 6 a1 a2 0.01 f +v s 7 4 a b c figure 20. single supply half- and full-wave rectifier 4.5 v low dropout, low power reference the rail-to-rail performance of the AD820 can be used to pro vide low dropout performance for low power reference circuits pow ered with a single low voltage supply. figure 21 shows a 4.5 v refer ence using the AD820 and the ad680, a low power 2.5 v bandgap reference. r2 and r3 set up the required gain of 1.8 to develop the 4.5 v output. r1 and c2 form a low-pass rc filter to reduce the noise contribution of the ad680. 2 3 4 r2 80k (20k ) u1 ad680 ref common 4.5v output 2.5v output r3 100k (25k ) c3 10 f/25v 3 6 7 2 c1 0.1 f c2 0.1 f film u2 AD820 5v 2.5v 10mv 6 r1 100k 4 figure 21. single supply 4.5 v low dropout reference with a 1 ma load, this reference maintains the 4.5 v output with a supply voltage down to 4.7 v. the amplitude of the recovery transient for a 1 ma to 10 ma step change in load current is under 20 mv, and settles out in a few microseconds. output voltage noise is less than 10 v rms in a 25 khz noise bandwidth. low power three-pole sallen key low-pass filter the AD820?s high input impedance makes it a good selection for active filters. high value resistors can be used to construct low frequency filters with capacitors much less than 1 f. the AD820?s picoamp level input currents contribute minimal dc errors. figure 22 shows an example, a 10 hz three-pole sallen key filter. the high value used for r1 minimizes interaction with signal source resistance. pole placement in this version of the filter minimizes the q associated with the two-pole section of the filter. this eliminates any peaking of the noise contribution of resistors r1, r2, and r3, thus minimizing the inherent out- put voltage noise of the filter. frequency e hz 0.1 filter gain response e db 0 e10 e100 e20 e30 e40 e50 e60 e70 e80 e90 110 100 1k c2 0.022 f v out 0.01 f +v s v in 0.01 f ev s 3 2 4 7 6 AD820 r1 243k c3 0.022 f c1 0.022 f r2 243k r3 243k figure 22. 10 hz sallen key low-pass filter
rev. d ?15? AD820 outline dimensions mini-dip package (n-8) dimensions shown in inches and (millimeters) seating plane 0.125 (3.18) min 0.035 0.01 (0.89 0.25) 0.033 (0.84) nom 0.018 0.003 (0.46 0.08) 0.165 0.01 (4.19 0.25) 0.18 0.03 (4.57 0.75) 8 14 5 pin 1 0.10 (2.54) bsc 0.39 (9.91) max 0.25 (6.35) 0.31 (7.87) 0.011 0.003 (0.28 0.08) 15 0 0.30 (7.62) ref soic package (r-8) dimensions shown in millimeters (inches)
?16? c00873?0?5/02(d) printed in u.s.a. revision history location page data sheet changed from rev. c to rev. d. changeto soic package (r-8) drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to product description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 delete specifications for AD820a-3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 edits to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 edits to typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 AD820

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